In case of debugging of multiple cores, there are two mainly employed intercore JTAG connection methods; (1) serial connections (daisy chain and cascade connections) and (2) parallel switch connection (star type connection). While the serial connection is widely employed, the parallel switch connection has the following advantages; correspondable to the power-off of each CPU core, short JTAG communication route, enabling low operation frequency cores to be prevented from becoming bottlenecks and to be optimized in operation, etc.
FIG. 7 shows a diagram of a multiprocessor system (LSI) including an object core selection controlling circuit in itself and employing the parallel switch connection (refer to JP-A-2004-164367). A chip 301 includes plural CPUs 3070 and 3071, as well as debuggers 3080 and 3081 that debug the CPUs 3070 and 3071. Furthermore, the chip 301 includes TAP controllers 3090 and 3091 that control the debuggers 3080 and 3081, a selection circuit 310 that selects at least one of the CPUs to be debugged, and a set of terminals including terminals 302 to 306. The CPUs 3070 and 3071 are connected to the debuggers 3080 and 3081, respectively and the debuggers 3080 and 3081 are connected to the TAP controllers 3090 and 3091, respectively. The selection circuit 310 is connected between each of the TAP controllers 3090 and 3091 and each of the terminals 302 to 306. The terminals 302 to 306 are connected to a debugger, not shown, such as an ICU or the like conforming to the JTAG standard, respectively.
The selection circuit 310 includes a primary TAP controller 400, a register 401, AND circuits 402 to 405, and selectors 406 and 407. One of the inputs of the AND is connected to the terminal 305 and the other input thereof is connected to the register 401. The output terminal thereof is connected to the TDI terminal of the TAP controller 3090, respectively. One of the inputs of the AND circuit 404 is connected to the terminal 304 and the other input thereof is connected to the register 401. The output terminal thereof is connected to the TMS terminal of the TAP controller 3091. And one of the inputs of the AND circuit 405 is connected to the terminal 305 and the other input thereof is connected to the register 401. The output terminal thereof is connected to the TDI terminal of the TAP controller 3091. One of the input terminals of the selector 406 is connected to the TDO terminal of the TAP controller 3090 and the other input terminal thereof is connected to the TDO terminal of the TAP controller 3091 and the output terminal thereof is connected to the terminal 306 through the selector 407.
In this configuration, the selection circuit 310 selects the CPU 3070 or 3071 to be debugged under the control of the primary TAP controller 400. The primary TAP controller 400 is kept connected to a JTAG signal in operation. Each of the TAP controllers 3090 and 3091 operates a TAP controller specified according to the select signal generated by the primary TAP controller 400.
Inn this case, the primary TAP controller 400 specifies the multicore extension register 401 according to the signal from the IR register (instruction register). Then, the primary TAP controller 400 sets a value in the extension register 401 through a DR register to debug either or both of the CPUs 3071 and 3072. Consequently, the CPU 3070 or 3071 is selected for debugging or both of the CPUs 3070 and 3071 are debugged simultaneously.